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mosel vitelic 1 v62c2181024 2.3 volt 128k x 8 static ram preliminary v62c2181024 rev. 1.3 august 1999 features n high-speed: 55, 70, 85, 100 ns n ultra low dc operating current of 1 m a (max.) ttl standby: 5 m a (max.) cmos standby: 1 m a (max.) n fully static operation n all inputs and outputs directly compatible n three state outputs n ultra low data retention current (v cc = 2v) n automatic power-down when deselected n single +3v 10% power supply n extended operating voltage: 2.3v?.7v n packages 32-pin tsop (standard) 32-pin 400 mil soj 32-pin 440 mil sop (525 mil pin-to-pin) description the v62c2181024 is a low power cmos static ram organized as 131,072 words by 8 bits. easy memory expansion is provided by an active low ce1 , and active high ce2, an active low oe , and three static i/o?. this device has an automatic power-down mode feature when deselected. device usage chart operating temperature range package outline access time (ns) power temperature mark t w r 557085100 l 0 c to 70 c blank ?0 c to +85 c i functional block diagram row decoder saense amp 1024 x 1024 column decoder input buffer control circuit a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 2181024 01 i/o 0 i/o 7 oe we ce1 ce2
2 v62c2181024 rev. 1.3 august 1999 mosel vitelic v62c2181024 pin descriptions a 0 ? 16 address inputs these 17 address inputs select one of the 128k x 8 bit segments in the ram. ce 1 , ce 2 chip enable inputs ce 1 is active low and ce 2 is active high. both chip enables must be active to read from or write to the device. if either chip enable is not active, the device is deselected and is in a standby power mode. the i/o pins will be in the high-impedance state when deselected. oe output enable input the output enable input is active low. when oe is low with ce low and we high, data of the selected memory location will be available on the i/o pins. when oe is high, the i/o pins will be in the high impedance state. we write enable input an active low input, we input controls read and write operations. when ce and we inputs are both low, the data present on the i/o pins will be written into the selected memory location. i/o 0 ?/o 7 data input and data output ports these 8 bidirectional ports are used to read data from and write data into the ram. v cc power supply gnd ground pin configurations (top view) 32-pin soj/sop 32-pin tsop (standard) 132 2181024 02 2 31 3 30 429 528 6 27 7 26 825 924 10 23 11 22 12 21 13 20 14 19 15 18 16 17 a 16 a 14 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 i/o 0 i/o 1 i/o 2 gnd nc a 15 ce 2 we a 13 a 8 a 9 a 11 oe a 10 ce 1 i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 v cc a11 a9 a8 a13 we ce2 a15 vcc nc a16 a14 a12 a7 a6 a5 a4 oe a10 ce1 i/o7 i/o6 i/o5 i/o4 i/o3 gnd i/o2 i/o1 i/o0 a0 a1 a2 a3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 2181024 03
mosel vitelic v62c2181024 3 v62c2181024 rev. 1.3 august 1999 part number information absolute maximum ratings (1) note: 1. stresses greater than those listed under ?bsolute maximum ratings?may cause permanent damage to the device. this is a stre ss rating only and functional operation of the device at these or any other conditions above those indicated in the operational se ctions of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliabili ty. symbol parameter commercial industrial units v cc supply voltage -0.5 to +4 -0.5 to +4 v v n input voltage -0.5 to +4 -0.5 to +4 v v dq input/output voltage applied v cc + 0.5 v cc + 0.5 v t bias temperature under bias -10 to +125 -65 to +135 c t stg storage temperature -55 to +125 -65 to +150 c sram family c = cmos process 62 = standard 21 = 3.0v operating voltage 1024k organization pkg speed 2181024 05 62 c 8 21 1024 mosel-vitelic manufactured v 8 = 8-bit 35 ns 70 ns temp. blank = 0 c to 70 c i = -40 c to +85 c l = low power ll = low low power t = tsop standard r = 400 mil soj w = 440 mil sop (525 mil pin-to-pin) density pwr. capacitance* t a = 25 c, f = 1.0mhz note: 1. this parameter is guaranteed and not tested. truth table note: x = don? care, l = low, h = high symbol parameter conditions max. unit c in input capacitance v in = 0v 6 pf c out output capacitance v i/o = 0v 8 pf mode ce 1 ce 2 oe we i/o operation standby h x x x high z standby x l x x high z output disable l h h h high z read lhlh d out write l h x l d in
4 v62c2181024 rev. 1.3 august 1999 mosel vitelic v62c2181024 dc electrical characteristics (over all temperature ranges, v cc = 3v 10%) notes: 1. these are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. v il (min.) = -3.0v for pulse width < t rc /2. 3. f max = 1/t rc . symbol parameter test conditions min. typ. max. units v il input low voltage (1,2) -0.5 0.8 v v ih input high voltage (1) 2.2 v cc +0.5 v i il input leakage current v cc = max, v in = 0v to v cc 1 m a i ol output leakage current v cc = max, ce 1 = v ih , v out = 0v to v cc 1 m a v ol output low voltage v cc = min, i ol = 2ma 0.4 v v oh output high voltage v cc = min, i oh = -2ma 2.4 v symbol parameter min. max. units i cc operating power supply current, ce 1 = v il , ce 2 = v ih , output open, v cc = max., f = 0 ?ma i cc1 average operating current, ce 1 = v il , ce 2 = v ih , output open 15 30 i cc2 average operating current, ce 1 = v il , ce 2 = v cc ?0.2, output open, v cc = max., f = f max (3) ?ma i sb ttl standby current ce 1 3 v ih , ce 2 v il , v cc = max. 0.6 ma i sb1 cmos standby current, ce 1 3 v cc ?0.2v, ce 2 0.2v, v in 3 v cc ?0.2v or v in 0.2v, v cc = max. ? m a l? ac test conditions ac test loads and waveforms input pulse levels 0.6 to 2.2v input rise and fall times 5 ns timing reference levels 1.4v output load see below * includes scope and jig capacitance c l = 30pf + 1ttl load (70, 85ns) c l = 100pf + 1ttl load (100ns) c l * 2181024 06
mosel vitelic v62c2181024 5 v62c2181024 rev. 1.3 august 1999 data retention characteristics notes: 1. t rc = read cycle time low v cc data retention waveform (1) (ce 1 controlled) symbol parameter min. max. units v dr v cc for data retention ce 1 3 v cc ?0.2v, ce 2 0.2v, v in 3 v cc ?0.2v, or v in 0.2v 2.0 v i ccdr data retention current ce 1 3 v dr ?.2v, ce 2 0.2v, v in 3 v cc ?0.2v, or v in 0.2v ? m a l1 t cdr chip deselect to data retention time 0 ns t r operation recovery time (see retention waveform) t rc (1) ?s v cc 2181024 07 data retention mode ce 1 3 v cc ?0.2v ce 1 2.2v 2.2v 2.7v t cdr t r v dr 3 2v 2.7v
6 v62c2181024 rev. 1.3 august 1999 mosel vitelic v62c2181024 ac electrical characteristics (over all temperature ranges) read cycle write cycle parameter name parameter -55 -70 -85 -100 unit min. max. min. max. min. max. min. max. t rc read cycle time 55 70 85 100 ns t aa address access time 55 70 85 100 ns t acs1 chip enable access time 55 70 85 100 ns t acs2 chip enable access time 55 70 85 100 ns t oe output enable to output valid 35 40 40 50 ns t clz1 chip enable to output in low z 10 10 10 10 ns t clz2 chip enable to output in low z 10 10 10 10 ns t olz output enable to output in low z 5???ns t chz chip disable to output in high z 25 30 35 40 ns t ohz output disable to output in high z 25 25 30 35 ns t oh output hold from address change 10 10 10 10 ns t pu power up time 0???ns t pd power down time 55 70 85 100 ns parameter name parameter -55 -70 -85 -100 unit min. max. min. max. min. max. min. max. t wc write cycle time 55 70 85 100 ns t cw1 chip enable to end of write 45 60 70 80 ns t cw2 chip enable to end of write 45 60 70 80 ns t as address setup time 0???ns t aw address valid to end of write 45 60 70 80 ns t wp write pulse width 45 50 60 70 ns t wr write recovery time 5???ns t whz write to output high-z 25 30 35 40 ns t dw data setup to end of write 25 30 35 40 ns t dh data hold from end of write 0???ns t ow output active from end of write 5???ns
mosel vitelic v62c2181024 7 v62c2181024 rev. 1.3 august 1999 switching waveforms (read cycle) read cycle 1 (1, 4, 5, 7) read cycle 2 (1, 4, 6, 7) read cycle 3 (1, 4, 6, 7) address data valid t rc d out t aa t oh 2181024-09 ce1 oe d out supply current t rc t ace t oe t chz t pd t clz t pu 50% 50% i cc i sb t ohz t olz 2181024 10 data valid 2181024 11 ce2 oe d out supply current t rc t ace t oe t chz t pd t clz2 t pu 50% 50% i cc i sb t ohz t olz data valid
8 v62c2181024 rev. 1.3 august 1999 mosel vitelic v62c2181024 switching waveforms (write cycle) write cycle 1 (we controlled) (8, 9) write cycle 2 (ce1 controlled) (8, 9) 2181024 12 t aw t wr t dw t dh t as t whz t ow address we input output t wc t wp data valid 2181024 13 t aw t wr t as t wz t dh t dw address ce1 we input output t wc t cw t wp data valid
mosel vitelic v62c2181024 9 v62c2181024 rev. 1.3 august 1999 write cycle 3 (ce2 controlled) (8, 9) notes: 1. the internal write time of the memory is defined by the overlap of ce 1 and ce 2 active and we low. all signals must be active to initiate and any one signal can terminate a write by going inactive. the data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 2. t wr is measured from the earlier of ce 1 or we going high, or ce 2 going low at the end of the write cycle. 3. during this period, i/o pins are in the output state so that the input signals of opposite phase to the outputs must not be a pplied. 4. oe = v il or v ih . however it is recommended to keep oe at v ih during write cycle to avoid bus contention. 5. if ce 1 is low and ce 2 is high during this period, i/o pins are in the output state. then the data input signals of opposite phase to the outputs must not be applied to them. 6. t cw is measured from ce 1 going low or ce 2 going high to the end of write. 2181024 14 t aw t wr t as t wz t dh t dw address ce2 we input output t wc t cw t wp data valid
10 v62c2181024 rev. 1.3 august 1999 mosel vitelic v62c2181024 package diagrams 32-pin 440 mil sop (525 mil pin-to-pin) 32-pin tsop (standard) 0.556 0.012 [14.12 0.305] 0.525 [13.34] max. 0.822 [20.88] max. 0.806 0.008 [20.47 0.203] 0.108 0.008 [2.74 0.203] 0.118 [3.00] max. 0.008 +0.004 ?.002 0.028 [0.711] 0.002 [0.051] max. 0.450 0.008 [11.43 0.203] 0.031 0.008 [0.787 0.203] 0? 0.098 [2.50] max 0.10 [2.54] max. 0.004 [0.102] max. 0.050 [1.27] 0.018 0.004 [0.457 0.102] units in inches [mm] 0.032 [0.813] typ. 0.020 [0.508] sbc 0.003 [0.076] max. 0.020 [0.508] max. 0.024 0.004 [0.610 0.102] seating plane 0.010 [.254] see detail ? detail ? 0.724 typ. (0.728 max.) [18.39 typ. (18.49 max)] 0.787 0.008 [19.99 0.203] 0.009 0.002 [0.229 0.051] 0.315 typ. (0.319 max.) 0.800 typ. (0.810 max.) 0.035 0.002 [0.889 0.051] 0.047 [1.19] max. 0.005 min. 0.007 max. 0.127 min. 0.178 max. units in inches [mm]
mosel vitelic v62c2181024 11 v62c2181024 rev. 1.3 august 1999 notes
mosel vitelic worldwide offices v62c2181024 ? copyright 1998, mosel vitelic inc. 8/99 printed in u.s.a. mosel vitelic 3910 n. first street, san jose, ca 95134-1501 ph: (408) 433-6000 fax: (408) 433-0952 tlx: 371-9461 the information in this document is subject to change without notice. mosel vitelic makes no commitment to update or keep cur- rent the information contained in this document. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of mosel-vitelic. mosel vitelic subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applica- tions. mosel vitelic does not do testing appropriate to provide 100% product quality assurance and does not assume any liabil- ity for consequential or incidental arising from any use of its prod- ucts. if such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. u.s. sales offices u.s.a. 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0952 hong kong 19 dai fu street taipo industrial estate taipo, nt, hong kong phone: 852-2666-3307 fax: 852-2770-8011 taiwan 7f, no. 102 min-chuan e. road, sec. 3 taipei phone: 886-2-2545-1213 fax: 886-2-2545-1209 no 19 li hsin rd. science based ind. park hsin chu, taiwan, r.o.c. phone: 886-3-579-5888 fax: 886-3-566-5888 singapore 10 anson road #23-13 international plaza singapore 079903 phone: 65-3231801 fax: 65-3237013 japan wbg marive west 25f 6, nakase 2-chome mihama-ku, chiba-shi chiba 261-7125 phone: 81-43-299-6000 fax: 81-43-299-6555 ireland & uk block a unit 2 broomfield business park malahide co. dublin, ireland phone: +353 1 8038020 fax: +353 1 8038049 germany (continental europe & israel) 71083 herrenberg benzstr. 32 germany phone: +49 7032 2796-0 fax: +49 7032 2796 22 northwestern 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0952 northeastern suite 436 20 trafalgar square nashua, nh 03063 phone: 603-889-4393 fax: 603-889-9347 southwestern 302 n. el camino real #200 san clemente, ca 92672 phone: 949-361-7873 fax: 949-361-7807 central & southeastern 604 fieldwood circle richardson, tx 75081 phone: 972-690-1402 fax: 972-690-0341

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